Review of: "transistor nMOS (with ultra-low power consumption, energy-efficient computing, during the subthreshold range)"

Qeios 17 (67307_76234):1 _ 2 (2024)
  Copy   BIBTEX

Abstract

Note: The field-effect tunnel transistor nMOS is an experimental type of transistor. Even if its structure is very similar to a metal-oxide semiconductor field-effect transistor nMOS , the basic switching mechanisms in these two transistors differ from each other; nMOS instead of exhibiting thermionic emission modulation, changes through a quantum tunnel modulation 12> They change through a dam. The field-effect tunneling transistor nMOS, as an alternative to conventional CMOS by enabling the voltage supply (VDD) with ultra-low power consumption, enables energy-efficient computing during the sub-threshold slope (SS) range. This type of device has a reverse-bias gate structure, which is usually called a tunnel field-effect transistor nMOS. For low power applications, nMOS is considered. This device has less static leakage current than a MOSFET and is more resistant to SCEs. The most outstanding feature of nMOS is the capacity to produce a reverse subthreshold swing (SS) of less than the 60 mV/decade thermal limit (at 300 K), which is related to common reverse mode nMOSs. A pseudo-thermal SS is achievable because the drain current in nMOSs is generated by source-to-channel carrier injection, which is often under the band tunneling radius. It is placed in the quantum mechanical band (BTBT). Transistor speed nMOS is proportional to the current. The higher the current, the faster the transistor will be able to amplify and charge (the sequential capacitor voltage). For a given transistor speed and maximum acceptable subthreshold leakage, the subthreshold slope thus defines a minimum threshold voltage. Decreasing the threshold voltage is an essential part of the idea to scale the constant amount of nMOS to overcome some challenges associated with the nMOS structure, such as its need for ultra-sharp doping profiles; however, such devices may suffer from gate leakage due to the presence of large vertical fields in the nMOS transistor structure.

Author's Profile

Afshin Rashid
Islamic Azad University Science and Reserch Branch Tehran

Analytics

Added to PP
yesterday

Downloads
2 (#96,754)

6 months
2 (#96,501)

Historical graph of downloads since first upload
This graph includes both downloads from PhilArchive and clicks on external links on PhilPapers.
How can I increase my downloads?